ASIC Senior Physical Design Engineer
2026-10-22
Semiconductor supplier KD provides innovative high-speed optical networking for harsh environments. Making multi gigabit communications over fiber optics a reality, KD technology supplies multi Gb/s optical links for automotive, industrial, and home networks.
Founded in 2010 in Madrid, Spain, KD has about 85 employees. We are in full expansion due to the development of innovative products in the sector and the creation of a unique factory in Spain.
As a result, we are seeking a highly skilled and motivated ASIC Senior Physical Design Engineer to join our backend implementation team. The ideal candidate will have hands-on experience in full RTL-to-GDSII flow using Synopsys tools (Design Compiler, IC Compiler II, Fusion Compiler, PrimeTime, TestMax ATPG), with a strong focus on advanced technology nodes (28nm and FinFET). You will be responsible for delivering high-quality, timing-closed, DRC/LVS-clean layouts for complex digital SoCs.
These are your tasks:
As R&D Project Manager you will support our R&D team leaders on the accomplishment of the tasks intended to develop our family of advanced optical transceiver ICs on time & within budget, in accordance with the goals set up by the company and the commitments related with public grant programs.
Perform RTL-to-GDSII implementation using Synopsys Design Compiler and ICC2, or Fusion Compiler including:
Logic synthesis.
Floorplanning.
Placement and CTS.
Routing and ECO closure.
Run Static Timing Analysis (STA) using PrimeTime to achieve timing closure across multiple corners and modes.
Power and EM/IR drop analysis using RedHawk.
Collaborate closely with RTL design team to optimize PPA.
Perform DFT insertion coordination with the design team.
Conduct Formal Verification to ensure logical equivalence with Formality.
Run and debug Physical Verification checks (DRC/LVS/ERC/Antenna) using IC Validator.
Write and maintain automation scripts using Tcl to streamline PD workflows and improve productivity.
Support physical sign-off processes including timing, power, signal integrity, and layout checks.
What you bring with you:
Requirements:
Bachelor’s or Master’s degree in Electronic Engineering, Computer Science, or a related field.
10+ years of experience in physical design, preferably with Synopsys EDA tools.
Strong understanding of ASIC design flow from RTL to GDSII.
Experience working at 28 nm and/or FinFET technology nodes.
Hands-on experience with Synopsys Physical Design flow.
Proficiency in Tcl scripting for flow automation.
Strong problem-solving skills and ability to work in a fast-paced environment.
Skills:
Low power design techniques (e.g., UPF/CPF).
Experience with multi-voltage designs.
Test pattern generation using TestMax ATPG.
Generation of Extracted Timing Models (ETM) of analog blocks.
Personal Profile:
Continuous search for technical excellence.
Passion for learning from experience.
Critical and constructive attitude.
Capability to accept system design responsibilities.
Proactive (problem solving) attitude,
Team membership attitude.
With us you can expect:
Development and growth: We offer development and training opportunities in a fast-growing start-up company.
Financial stability: With us you receive performance-related pay, health insurance as well as other company benefits.
Work-life balance: An essential part of our company culture. We offer the possibility of hybrid work and flexible working hours and the opportunity to work in a modern workplace in an excellent location in Madrid (Tres Cantos).
Working together: we are a friendly team with a shared passion for technology. We focus on building personal connections through team events and networking activities between teams.
Employment benefits:
Flexible working hours, intensive working hours on Fridays and the three summer months.
10 hours of telework per week.
Free Medical insurance for the employee and discounts for family members.
English/Spanish classes free.
Ticket Restaurant option.
Company social events.
Training plan and development opportunities.
Employment conditions:
Indefinite full-time contract.
24 working days holiday.
Dynamic and collaborative work environment, with ambitious and innovative projects.
Flat hierarchies and open communication.
A very good working atmosphere with competent, motivated and friendly colleagues, open to the international level.
Location: Madrid (Tres Cantos).
Salary: To be negotiated based on candidate´s experience.
- Location
- Madrid-Spain
- Contract type
- Full-Time Regular
- Experience
- +10 years
- Education
- BSc or MSc in Electronic Engineering, Computer Science